PLX PCI9656 RDK Rapid Development Kit

Description: FEATURE SUMMARY • Bus Mastering interface between a 64-bit, 66 MHzPCI Bus and 32-bit, 66 MHz processor Local Bus• PCI r2.2-compliant• Supports Vital Product Data (VPD)• Supports PCI Power Management r1.1,including D3cold PME generation for PC 2001modem and network communicationsadapter compliance• PICMG 2.1 CompactPCI® r1.0 Hot SwapReady• PCI Hot Plug r1.0 compatible• Direct connection to three processor Local Bustypes• M Mode—Motorola MPC850, MPC860,PowerPC 801• C Mode (non-multiplexed address/data)—Intel i960, DSPs, custom ASICs and FPGAs,and others• J Mode (multiplexed address/data)—Intel i960, IBM PowerPC 401, DSPs,IOP 480, and others• Asynchronous clock inputs for PCI andLocal Buses• 272-pin, 27 x 27 mm, 1.27 mm ball pitch PBGA• Low-power CMOS 2.5V core, 3.3V I/O• 3.3 and 5.0V-tolerant PCI and Local Busoperation• Industrial Temperature Range operation• IEEE 1149.1 JTAG boundary scan• Three data transfer modes—Direct Master, DirectSlave, and DMA1• Direct Master—Transfer data between aMaster on the Local Bus and a PCI Bus device• Two Local Bus address spaces to the PCIBus—one to PCI memory and one to PCI I/O• Generates all PCI memory and I/Otransaction types, including MWI andType 0/1 configuration• Read Ahead, Programmable Read PrefetchCounter (all modes)• MPC850/MPC860 Delayed Read and IDMAsupport (M mode)• Direct Slave—Transfer data between a Masteron the PCI Bus and a 32-, 16-, or 8-bit LocalBus device• Two general-purpose address spaces to theLocal Bus and one expansion ROM addressspace• Delayed Read, Delayed Write, Read Ahead,Posted Write, Programmable Read Prefetchcounter• Programmable READY# timeout andrecovery• DMA—PCI 9656 services data transferdescriptors, mastering on both buses duringtransfer• Two independent channels• Block Mode—Single descriptor execution• Scatter/Gather Mode• Descriptors in PCI or Local Bus memory• Linear descriptor list execution• Dynamic DMA descriptor RingManagement with Valid bitsemaphore control• Burst descriptor loading• Hardware EOT/Demand controls tostop/pause DMA in any mode• Programmable Local Bus burst lengths,including infinite burst• Six independent, programmable FIFOs—DirectMaster Read and Write, Direct Slave Read andWrite, DMA Channel 0 and 1 1 INTRODUCTION1.1 COMPANY AND PRODUCTBACKGROUNDPLX Technology, Inc., the leading supplier of highperformancePCI-to-Local Bus chips and software,supports OEM customers in a wide variety ofapplications including embedded networking products,such as routers and switches, PC workstations andservers, adapter boards, and industrialimplementations, such as CompactPCI and PMC.An active participant in industry standard committees,including the PCI SIG, PICMG, CompactPCI,I2O SIG, and the RapidIO trade association, PLXmaintains active development and cross-marketingpartnerships with industry leaders such as Intel, IBM,Hewlett-Packard, Motorola, WindRiver, and others.PLX provides customers with the complete PCIsolution, which results in faster time to market andlower development costs. This complete solutionconsists of high-performance I/O chips, PCI ReferenceDesign Kits (RDK), the PCI Hardware DevelopmentKit (HDK) CD-ROM collection, PCI SoftwareDevelopment Kits (SDK), and third-party developmenttools through the PLX Partner Program. Our referenceboards, “C” API libraries, software debug tools, RTOSand Windows device drivers enable customers toquickly bring new designs to production withoutworrying about the complexities of implementing PCIhardware, software and I2O. New tools, applicationnotes and information updates are frequently added tothe PLX web site (http://www.plxtech.com).Serving the computer industry since 1986, PLX is theleading source of high-performance, I/O silicon,software, and development tools.1.2 DATA PIPE ARCHITECTURETECHNOLOGYPLX I/O accelerators feature PLX proprietary DataPipe Architecture™ technology. This technologyconsists of powerful, flexible engines for high-speeddata transfers, as well as intelligent messaging unitsfor managing distributed I/O functions.1.2.1 High-Speed Data TransfersData Pipe Architecture technology providesindependent methods for moving data—DirectTransfers and DMA.Regardless of the method chosen, Data PipeArchitecture technology data transfers support thefollowing:• PCI ↔ Local Bus burst transfers at the maximumbus rates• Unaligned transfers on both buses• On-the-fly Local Bus Endian conversion• Programmable Local Bus wait states• Parity checking on both buses1.2.1.1 Direct TransfersData Pipe Architecture technology Direct Transfersare used by a master on either the PCI or Local Bus tomove data through the I/O accelerator to a device onthe other bus. The master takes responsibility formoving the data either into the I/O accelerator on awrite or out of the I/O accelerator on a read. The I/Oaccelerator is responsible for moving the data out tothe target device on a write, or in from the targetdevice on a read.1.2.1.1.1 Direct MasterWhen a master on the local processor bus uses DirectTransfer, this is a Direct Master transfer. The I/Oaccelerator is a master on the PCI Bus. Data PipeArchitecture technology provides independent FIFOsfor Direct Master Read and Write transfers. It alsosupports multiple independent Direct Master LocalBus address spaces for mapping to PCI addresses, asshown in Figure 1-1.Direct Master transfers support generation of all PCImemory and I/O transaction types, including Type 0/1cycles for system configuration. https://docs.broadcom.com/doc/pci9656RDK-LITE_HRM_With_Schematic_19Jan06 https://www.drvhub.net/devices/other-devices/plx-technology-inc/plx-pci-9656-rdk-lite-board

Price: 399 USD

Location: Budapest, BP

End Time: 2024-12-27T14:12:26.000Z

Shipping Cost: 100 USD